US-China AI Competition Daily Briefing

 

US-China AI Competition Daily Briefing- 

1. Financial & Investment Controls: US Treasury Issues COINS Act Proposed Rule

Following statutory expansion under the FY2026 National Defense Authorization Act (NDAA), the U.S. Department of the Treasury officially published its proposed regulations implementing the COINS Act:

• Targeting Outbound VC/PE Capital: The rule establishes a formal regulatory system managed by Treasury requiring U.S. venture capital firms, private equity funds, and individual investors to notify Treasury or face strict prohibitions on transactions involving Chinese entities working on advanced AI systems, microelectronics, quantum, and high-performance computing (HPC).
  
  
• De Minimis Threshold & Knowledge Standards: The regulation sets a $50,000 threshold for covered deals and enforces a strict "reasonable and diligent inquiry" due-diligence standard for U.S. Limited Partners (LPs) investing in foreign venture capital funds.
  
  
• Closing the Indirect Financing Loophole: Treasury officials explicitly noted that the rule targets capital that brings U.S. managerial expertise, board seats, and networking networks alongside dollars to Chinese AI startups—further isolating Chinese chip designers and AI labs from Western venture capital ecosystems.
  
  

2. Geopolitical Alignment & Pre-Summit Messaging: The Distillation Battle

Ahead of expected high-level bilateral diplomatic exchanges between Washington and Beijing, statements from U.S. officials and former tech executives highlight the framing of the AI conflict:

• Official Rhetoric on Model Distillation: Senior U.S. trade officials reaffirmed that "model distillation"—the practice of using automated API calls on Western closed-source models (like OpenAI or Anthropic) to extract reasoning traces and train secondary Chinese models—remains a primary focus for U.S. policy. U.S. officials assert that Chinese firms use synthetic data extraction to bypass pre-training capital costs, while Beijing defends distillation as standard, widespread industry practice.
  
  
• Commercial Risk of "Zero-Cost" Models: Former Google CEO Eric Schmidt publicly noted that while Chinese frontier models trail top U.S. benchmarks by approximately six months, China's aggressive strategy of offering open-weights and low-cost or free models globally poses a long-term commercial challenge to Western AI subscription models.
  
  

3. Open-Source Ecosystem: DeepSeek Releases DeepInfer Framework

Adding to its software expansion alongside TileLang, Hangzhou-based DeepSeek open-sourced its internal large-scale inference platform, DeepInfer:

• Dual-Backend Support (Nvidia & Ascend): The framework provides native, unified execution paths across both Nvidia CUDA hardware and Huawei Ascend NPUs.
  
  
• Production-Grade Features: DeepInfer packages distributed multi-node inference, speculative decoding, and structured output engines designed to maximize token throughput while lowering serving energy costs.
  
  
• Software Bridge to Domestic Hardware: By releasing optimized inference frameworks alongside open-weight models, DeepSeek continues to lower the technical barrier for enterprise developers migrating workloads onto sovereign Chinese hardware stacks (like the Ascend 950 series).
  
  

4. Hardware Supply Chain: Regional Labor Agreements & Equipment Sourcing

• Micron Taiwan Labor Resolution: Memory giant Micron and its Taiwan union resolved mediation disputes and signed a comprehensive labor-management agreement at its Taichung operations. As the world's third-largest memory producer, Micron's Taiwan facilities serve as a manufacturing node for High-Bandwidth Memory (HBM) used in global AI accelerators.
  
  
• Taiwanese Tooling Alternatives: TSMC and Taiwanese foundry ecosystems continue expanding efforts to qualify domestic and non-U.S. equipment and component suppliers to insulate advanced manufacturing lines against shifting global trade controls and export licensing delays.
  
  

Strategic Takeaway

The confrontation continues to shift from simple physical chip bans to a multi-layered technological containment strategy: the U.S. is blocking capital flows (via Treasury's COINS Act rules) and targeting synthetic distillation, while Chinese developers (DeepSeek, Huawei) are strengthening an open-source software stack (TileLang, DeepInfer) designed to maintain ecosystem growth regardless of Western hardware embargoes.

Technical Breakdown: DeepSeek DeepInfer Framework

DeepSeek’s open-sourcing of DeepInfer (under Apache 2.0) explicitly reveals the production-grade serving stack behind its flagship frontier model, DeepSeek-V4.1-Flash. Built on the lineage of vLLM with design inspirations from SGLang and TensorRT-LLM, DeepInfer operates as a model-specialized offline inference engine designed to maximize throughput and energy efficiency across multi-node clusters.

DeepInfer serves as an orchestrator that stacks DeepSeek’s specialized lower-level primitive libraries—FlashMLA, DeepGEMM, DeepEP, TileKernels, DeepSelect, and custom TileLang operators—under unified system-level scheduling abstractions.

                         DeepInfer Execution Architecture
  
     OFFLINE INFERENCE ENGINE & SERVING ABSTRACTIONS
 ┌────────────────────────────────────────────────────────────────────────┐
 │ • DSpark Confidence-Scheduled Speculative Decoding (Next-N=5)         │
 │ • Wide Expert Parallelism (EP64 / EP128) & EPLB Load Balancing         │
 │ • Sliding Window Attention (SWA) Bounded Replay                       │
 │ • Async CPU/GPU Pipeline & Deterministic Batch-Invariant Sampling     │
 └───────────────────────────────────┬────────────────────────────────────┘
                                     │
                     HARDWARE RUNTIME BACKEND COMPILATION
                 ┌───────────────────┴───────────────────┐
                 ▼                                       ▼
 ┌───────────────────────────────┐       ┌───────────────────────────────┐
 │ Nvidia CUDA Backend           │       │ Huawei Ascend Backend         │
 │ • CUDA 13 Toolchain           │       │ • CANN 9.2 Software Toolkit   │
 │ • SM100 (Blackwell) Target    │       │ • Ascend 950 Series Target    │
 │ • Native PTX / Cutlass Kernels│       │ • PTO / TileLang Compiler     │
 └───────────────────────────────┘       └───────────────────────────────┘

Core Architectural Features of DeepInfer

1. DSpark Speculative Decoding Engine

To combat decoding latency in massive Mixture-of-Experts (MoE) architectures, DeepInfer implements DSpark, a confidence-scheduled speculative decoding pipeline:

• Draft Token Generation: A small draft model proposes $N=5$ speculative tokens per step.
  
  
• Confidence-Scheduled Verification: Rather than evaluating all speculative branches, a specialized Confidence Head predicts each draft token's acceptance rate. DeepInfer dynamically truncates low-confidence paths, reducing verified draft tokens by ~30% (from 5.0 down to ~3.2–4.4) while preserving near-identical acceptance rates and saving significant compute.
  
  

2. Sliding Window Attention (SWA) Bounded Replay

During the prefill and decode stages of long-context generation, DeepInfer manages memory overhead through SWA Bounded Replay:

• On cache hits, the engine avoids full context recomputation by bounded-replaying only the final 128 tokens of the sliding-window attention state.
  
  
• This enforces a constant recomputation cost regardless of total context length, halving prefill compute requirements for long-context requests.
  
  

3. MoE Expert Parallel Load Balancing (EPLB)

DeepInfer orchestrates expert routing using Wide Expert Parallelism (Wide-EP):

• Decode Stage: Runs at extreme expert parallelism (EP64 to EP128) within high-bandwidth supernode domains.
  
  
• Prefill Stage: Constrains parallelism to EP2–EP8 to optimize for device memory limits. The engine leverages DeepEP to achieve token dispatch speeds reaching over 300 GB/s across cluster interconnects.
  
  

Comparative Performance Optimizations: Nvidia CUDA vs. Huawei Ascend NPUs

While DeepInfer abstracts model execution into a single Python/C++ pipeline, its underlying hardware optimization paths for Nvidia SM100 (Blackwell) and Huawei Ascend 950 diverge fundamentally in kernel execution, compilation targets, and system-level features.

                     CUDA vs. Ascend Architectural Matrix
  
  FEATURE / OPTIMIZATION     NVIDIA CUDA (SM100)            HUAWEI ASCEND (ASCEND 950)
 ┌──────────────────────────┬──────────────────────────────┬──────────────────────────────┐
 │ Required Software Tool   │ CUDA 13                      │ CANN 9.2                     │
 ├──────────────────────────┼──────────────────────────────┼──────────────────────────────┤
 │ Primary Kernel Engine    │ Cutlass / Native CUDA C++    │ TileLang / PTO Compiler      │
 ├──────────────────────────┼──────────────────────────────┼──────────────────────────────┤
 │ Deterministic Sampling   │ Fully Supported              │ Not Supported (Disabled)     │
 ├──────────────────────────┼──────────────────────────────┼──────────────────────────────┤
 │ Batch-Invariant Infer.   │ Fully Supported              │ Not Supported (Disabled)     │
 ├──────────────────────────┼──────────────────────────────┼──────────────────────────────┤
 │ MoE Dispatch Driver      │ DeepEP (CUDA IPC / NVLink)   │ DeepEP-Ascend (Lingqu Bus)   │
 ├──────────────────────────┼──────────────────────────────┼──────────────────────────────┤
 │ Memory Layout Scheme     │ Separated FP8 Quant Scaling  │ Co-located Quant Scale-Bias  │
 └──────────────────────────┴──────────────────────────────┴──────────────────────────────┘

1. Optimization Strategy on Nvidia CUDA (SM100 Target)

• Native Instruction Exploitation: On Nvidia Blackwell architectures, DeepInfer interfaces directly with CUDA 13 toolchains. Kernels leverage Tensor Memory Accelerator (TMA) asynchronous copies and Warp-Group Matrix Multiply-Accumulate (WGMMA) instructions to maximize Tensor Core occupancy.
  
  
• Deterministic Sampling & Batch Invariance: Nvidia execution paths support Batch-Invariant Inference and Deterministic Sampling. By eliminating floating-point non-determinism across varying dynamic batch sizes, Nvidia clusters achieve 100% reproducible token generation for identical seeds.
  
  
• Hardware Utilization: Independent hardware profiling (such as benchmarks by SemiAnalysis) confirms Nvidia H100/SM100 systems achieve a median 46.8% bandwidth utilization ratio under memory-bound GEMM shapes, benefiting from mature CUDA drivers and power-state stability.
  
  

2. Optimization Strategy on Huawei Ascend NPUs (Ascend 950 Target)

• TileLang / CANN 9.2 Abstraction: Because native Ascend C lacks the extensive operator libraries of CUDA, DeepInfer relies on TileLang compiled through Huawei’s CANN 9.2 toolkit and the PTO compiler. TileLang automatically generates custom NPU primitives that map directly to Ascend's Dual-Core (Cube Core + Vector Core) architecture.
  
  
• Memory Co-location & Layout Adjustments: To bypass memory bandwidth bottlenecks on SMIC-manufactured 7nm silicon, DeepInfer alters tensor layout rules on Ascend. While CUDA stores quantized values and FP8 scaling factors in separate VRAM locations, DeepInfer co-locates scaling factors directly alongside tensor memory buffers on Ascend to minimize L1/UB cache fetch penalties.
  
  
• Feature Restrictions & Utilization: On Ascend 950 NPU clusters, DeepInfer explicitly disables Deterministic Sampling and Batch-Invariant Inference due to NPU dynamic shape limitations and speculative decoding constraints. Under memory-bound GEMM shapes, Ascend 950 chips achieve a median 41.5% theoretical bandwidth utilization. However, on compute-heavy FP8/BF16 dense GEMMs, DeepSeek's DeepGEMM-Ascend achieves up to 99.7%–99.8% of theoretical peak FLOPS.
  
  

Performance Benchmarks & Operational Limitations

DeepSeek self-reported high-concurrency production benchmarks for DeepSeek-V4.1-Flash running on DeepInfer:

• Decode Throughput (64-GPU Cluster): Running at EP64DP64 with $N=3$ speculative decoding, the engine achieved >25,000 output tokens/sec/GPU at 256 requests per rank, sustaining nearly 100 tokens/sec per individual user stream.
  
  
• Prefill Throughput (4-GPU Cluster): Running at EP4DP4, prefill processing reached ~60,000 non-cached tokens/sec/GPU at 4,096 tokens per rank.
  
  

Production Scoping Limitations

DeepSeek explicitly clarifies that the public DeepInfer repository contains offline inference components only. To deploy DeepInfer in an online enterprise production environment, engineering teams must build or integrate three missing infrastructure layers:

1. External Distributed KV-Cache Store: The engine excludes full persistent KV-cache store management.
   
   
2. Prefill/Decode (P/D) Disaggregation Router: P/D cluster splitting and disaggregated service routing are omitted.
   
   
3. Multi-Replica Load Balancer: Cross-copy data-parallel load balancing must be supplied externally.

1. Architectural Overview of Huawei CANN

CANN (Compute Architecture for Neural Networks) serves as Huawei’s core software stack connecting upper-level deep learning frameworks to underlying Ascend NPU hardware. Positioned symmetrically to Nvidia’s CUDA/CuDNN/TensorRT software layer, CANN exposes hardware compute resources while handling task graph compilation, driver management, memory allocation, and multi-NPU collective communication.

                     Huawei CANN Full-Stack Architecture
  
   FRAMEWORK LAYER         PyTorch / MindSpore / DeepSeek Runtime Tools
                                    │ (torch_npu / C++ APIs)
 ┌──────────────────────────────────▼──────────────────────────────────┐
 │ CANN SOFTWARE STACK                                                 │
 │                                                                     │
 │  ┌───────────────────────────────────────────────────────────────┐  │
 │  │ GE (Graph Engine) & PTO Compiler Pipeline                      │  │
 │  │  • Graph Fusion & Memory Reuse                                │  │
 │  │  • Static IR Code Gen & Task Stream Packaging                 │  │
 │  └──────────────────────────────┬────────────────────────────────┘  │
 │                                 ▼                                   │
 │  ┌───────────────────────────────────────────────────────────────┐  │
 │  │ Ascend Computing Language (ACL) Runtime                       │  │
 │  │  • Device Allocation • Memory Pools • Task Queue / Streams   │  │
 │  └──────────────────────────────┬────────────────────────────────┘  │
 │                                 ▼                                   │
 │  ┌───────────────────────────────────────────────────────────────┐  │
 │  │ Operators & Communication Libraries                           │  │
 │  │  • CANN Operator Libraries (ops-nn, ops-transformer, ops-math)│  │
 │  │  • HCCL (Huawei Collective Communication Library)             │  │
 │  └───────────────────────────────────────────────────────────────┘  │
 └─────────────────────────────────┬───────────────────────────────────┘
                                   ▼
   HARDWARE LAYER          Ascend NPU (Cube Cores, Vector Cores, Lingqu Bus)

Core Components

• Ascend Computing Language (ACL): Provides the C/C++ host API layer governing NPU device initialization, memory allocation, stream synchronization, and low-level kernel execution launches.
  
  
• Graph Engine (GE): The front-end graph compiler that ingests, optimizes, fuses, and converts compute graphs into hardware execution packages.
  
  
• CANN Operator Libraries: Highly tuned, low-level operator collections (ops-math, ops-nn, and ops-transformer) optimized for Ascend AI Cores.
  
  
• HCCL (Huawei Collective Communication Library): Manages multi-NPU gradient synchronization and inter-chip collective communication operations (such as AllReduce, AllGather, AllToAll, and P2P) over local HCCS connections and scale-out RoCE networks.
  
  

2. Native PyTorch NPU Backend Integration (torch_npu)

To integrate with PyTorch without modifying core PyTorch source code, Huawei developed torch_npu. This adapter hooks directly into PyTorch’s C++ extension system (torch::RegisterOperators and C10 Dispatcher registry) using PyTorch's native PrivateUse1 device interface.

                     PyTorch to CANN Operator Dispatch
  
   User Code                   torch.matmul(A, B).npu()
                                          │
                                          ▼
   PyTorch Dispatcher          C10 Dispatcher (PrivateUse1 Device Key)
                                          │
                                          ▼
   torch_npu Adapter           at::native::npu_matmul Interface
                                          │
                                          ▼
   CANN ACL Runtime            aclopCompileAndExecute() / Graph Node
                                          │
                                          ▼
   Ascend Hardware             Cube Core Exec (FP16/FP8 Matrix Engine)

Technical Integration Mechanisms

1. Device Registration: torch_npu registers torch.device("npu") alongside PyTorch's native cpu and cuda devices. API calls like .to("npu") or .npu() route data directly to NPU High-Bandwidth Memory (HBM).
   
   
2. Operator Mapping & Dispatch: When PyTorch executes a forward or backward pass, the C10 Dispatcher intercepts the operation and redirects execution to torch_npu's C++ bindings (torch_npu._C). These bindings map standard PyTorch operators (e.g., torch.matmul) to corresponding CANN ACL APIs (e.g., aclopCompileAndExecute or custom Ascend kernels).
   
   
3. NPUCachingAllocator: Implements a memory management scheme modeled after CUDA's caching allocator. It allocates large memory blocks directly from ACL runtime memory pools (aclrtMalloc) and serves small tensor allocations locally to eliminate device allocation overhead during runtime execution loops.
   
   
4. Execution Modes:
   
   
   • Eager Mode: Dispatches operators individually to multi-stream TaskQueues, allowing dynamic graph operations.
     
     
   • Graph Mode (torch.compile / NPUGraphs): Integrates TorchDynamo with an Inductor/GE backend to capture the compute graph, perform global operator fusion, and offload static graphs directly to NPU execution streams.
     
     

3. The PTO (Parallel Thread Optimization) Compiler Pipeline

The PTO (Parallel Thread Optimization) Compiler functions as the specialized IR-to-binary compilation engine within CANN's compiler infrastructure. While high-level DSLs (like Ascend C, TileLang, or Triton-Ascend) describe algorithm dataflow, PTO optimizes execution pipelines across Ascend's heterogeneous architecture (Cube Cores, Vector Cores, and Memory Transfer Engines).

                   PTO Compiler Transformation Pipeline
  
  High-Level DSL (TileLang / Ascend C / Triton)
                         │
                         ▼
  1. Frontend IR Parsing (MLIR / TVM AST Parsing)
                         │
                         ▼
  2. Memory Hierarchy Layout & Tiling
     (Global Memory ──► L1 Buffer ──► Unified Buffer / L0A/L0B/L0C Registers)
                         │
                         ▼
  3. Heterogeneous Scope Partitioning
     ┌───────────────────┴───────────────────┐
     ▼                                       ▼
  Cube Core Pipeline Scope                Vector Core Pipeline Scope
  (Matrix Multiplication)                 (Activations / Layernorm / Softmax)
     └───────────────────┬───────────────────┘
                         │
                         ▼
  4. Multi-Stage Pipeline Synchronization
     (MTE1/MTE2 Asynchronous Memory Pipeline & Lock/Flag Insertion)
                         │
                         ▼
  5. Code Generation & Assembly Emission
     (Produces Hardware .o Binary & Operator Task Strings)

Core Transformation Stages

1. Frontend IR Parsing: Translates input kernel code (from TVM IR, MLIR, or Ascend C ASTs) into a unified intermediate representation that preserves tensor shape bounds and loop attributes.
   
   
2. Layout & Tiling Transformation: Maps continuous high-level tensor dimensions to physical buffer hierarchies across Ascend silicon:
   
   
   • GM (Global Memory / HBM) $\rightarrow$ L1 Cache $\rightarrow$ UB (Unified Buffer) $\rightarrow$ L0 Matrix Registers (L0A, L0B, L0C).
     
     
3. Scope Partitioning & Execution Mapping: Splits kernel execution steps based on hardware engine type:
   
   
   • Cube Core Instructions: Scheduled for high-throughput matrix multiplication.
     
     
   • Vector Core Instructions: Scheduled for element-wise ops, normalization, and nonlinear activation functions.
     
     
4. Asynchronous Memory & Pipeline Synchronization: Inserts asynchronous Memory Transfer Engine (MTE) commands alongside synchronization flags (set_flag / wait_flag) to double-buffer memory transfers (MTE1: L1 to L0; MTE2: GM to L1/UB; MTE3: UB to GM). This hides memory latency behind matrix math execution.
   
   
5. Assembly Emission: Compiles optimized instructions down to machine code binaries (.o), which are wrapped into CANN Task Strings for execution by the ACL runtime.
   
   

Key Operational Characteristics

• Ecosystem Parity: Through torch_npu and CANN, models written in native PyTorch can be deployed on Ascend NPUs by modifying device target strings.
  
  
• Graph-Level Optimizations: Graph Mode and PTO compiler passes reduce CPU-to-NPU dispatch bottlenecks by capturing, fusing, and executing execution graphs as unified, static tasks.
  
  
• Native Custom Operators: Developers can compile custom, hardware-tuned kernels using high-level DSLs (such as TileLang or Ascend C) through PTO pipelines, enabling low-precision FP8/BF16 matrix execution without relying on closed CUDA libraries.

By Jugo Ikeji-Uju. 

admin@ubuntusafa.com 

sappertekinc@gmail.com

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